1. Field of the Invention
The present invention relates to a program controlled processor, and more particularly to a program skip operation control system used in a program controlled processor. More specifically, the present invention relates to a program skip operation control system used in a program controlled processor of the instruction prefetch type which includes a program memory and an instruction address register adapted to hold the address of an instruction to be fetched from the program memory, the instruction address register being capable of updating the address of an instruction so that during execution of one instruction the instruction to be next executed is fetched from the program memory.
2. Description of Related Art
A so-called instruction prefetch type microprocessor has been known as one of the program controlled processors. This instruction prefetch type microprocessor is designed so that each microinstruction is executed in one or two cycles. For this purpose, when each microinstruction is executed, a microinstruction to be executed next after the microinstruction being executed is fetched from a program memory. To ensure such an operation, an address register associated to the program memory is adapted to updateably prefetch an address of an instruction to be next fetched from the program memory.
In this instruction prefetch type microprocessor, branch operations are often required, similarly to other processors. To process such branch operations, the following two methods have been proposed. One of these methods is to break an address already prefetched in an address register as the address of an instruction to be next executed and to newly register a branch address. The other method is to execute an instruction of an address prefetched and then to enter a branch operation. The latter method is called a "delayed branch" hereinafter.
In order to carry out the former method, when a branch operation is conditionally or unconditionally established as the result of microinstruction decoding, it is necessary to invalidate the execution of instructions for the period in which the content of the address register already prefetched is rewritten to a branch address. This will lead to a decrease in the execution efficiency of a program including a number of branch instructions. In the delayed branch system, on the other hand, after a branch operation is established, an instruction of the address already prefetched is executed. Therefore, a program flow becomes complicated at some degree, but the branch operation itself will not directly decrease the processing efficiency.
On the other hand, a program sequence control is generally based either on a first method in which a program address is contained in a microinstruction code without exception, or on a second method in which addresses of microinstructions are controlled by an address generating circuit such as an address counter and an incrementer unless a branch is required, and only branch addresses are included in microinstructions. Comparing the two methods, the latter method is advantageous in a required capacity of a microinstruction storage memory.
In an instruction prefetch type microprocessor using the delayed branch system and carrying out the program sequence control with a program counter, when a program skip is performed, the following difficulty has been encountered. Namely, when a program skip condition is established, the processing of the next instruction address already prefetched will be attended with a problem similar to that in the branch processing as mentioned above. In addition, a very complicated interaction will be inevitably required between a modification of a program sequence control line and the content of a microinstruction being currently executed, particularly between the execution of the branched microinstruction and the skip operation. Therefore, a program has been subjected to various and many limitation, or a complicated control mechanism has been required. In fact, however, the program skip operation is very frequently combined with the branch operation.
In this circumstance, Japanese Post-examination Patent Publication No. 18738/1984 filed in the name of International Business Machine Corporation, claiming Convention priority based on U.S. patent application Ser. No. 50888 filed June 21, 1979 now U.S. Pat. No. 4,279,016, discloses a branch and interrupt system for a prefetched microprocessor. Specifically, a control of the delayed branch processing and interrupt has been proposed. However, the proposed system still includes such limitations in program and function that it is not allowable to program a branch command after another branch instruction of a program sequence width and that an interrupt operation is limited during execution of the branched command. Therefore, such a general structure is adopted that a program skip operation is carried out by means of internal interrupt. In other words, the proposed system still needs substantial limitation in program or a complicated control for processing a branch command.